As is generally known, conventional dynamic random access memory (DRAM) devices include memory arrays having memory cells arranged in rows and columns. Each of the memory cells are typically formed from a capacitor, which acts as the storage node, and an access device that couples the capacitor to a sense node at which the charge state of the capacitor is sensed and amplified by a sense amplifier. The sense node is typically represented by a digit line. The digit lines are grouped in complementary pairs that are coupled to a respective sense amplifier. One pair of digit lines represents a column of memory cells. The access devices for a row of memory cells are coupled to a word line, which when activated, couple the memory cells to the respective digit line.
As part of the process in accessing the memory cells, the pairs of digit lines are “precharged” by a precharge circuit in preparation for a memory cell access operation. Precharging equilibrates the voltage of the pairs of digit lines and sets the voltage of the digit lines to a precharge voltage level, which is generally one-half of the power supply voltage for the memory device. During the precharge operation, all of the word lines are grounded to ensure that the charge state stored by the memory cell capacitors are not altered. When the memory cells are accessed, a word line is activated to couple the memory cells of the row to the respective digit lines. Only one row of an array of memory cells is activated at a time, with the word lines of the other memory cells grounded to ensure that the access devices remain inactive. When coupled to the respective digit lines, the capacitors of the activated row of memory cells alter the voltage of the digit lines from the precharge voltage level. The change in voltage is detected by the sense amplifier coupled to the respective digit line and amplified.
As also generally known, memory devices, such as DRAMs, include redundant rows and columns of memory to replace defective rows and columns of memory. That is, the memory addresses for defective memory locations are remapped to the redundant memory. Thus, although a memory device may include some defective memory, it can nevertheless operate normally through the use of the redundant memory. For example, a well known failure mode occurs when a digit line is short circuited to a word line. As previously discussed, during a memory access operation, all of the word lines except for the row of memory cells being accessed are coupled to ground. Where a digit line and word line are short circuited, the digit line will be held to a ground potential. As a result, the low voltage level will be sensed by the sense amplifier and amplified, regardless of the voltage level of any of the memory cells of that column. Additionally, the additional load on the word line that is short circuited to the digit line may be such that the word line cannot achieve a sufficient voltage level in the region of the short circuit to couple the memory cells to the respective digit line. As a result, the memory cells of the shorted row in the vicinity of the short circuit are also defective. The defective column and row results in a failure pattern that produces a “cross” of defective memory cells. In many cases, assuming that the number of cross failures does not exceed the number of available rows and columns of redundant memory, the memory addresses of the defective memory cells can be remapped so that the memory device can be operated normally by using the redundant memory.
Having a sufficient amount of redundant memory, however, does not ensure that a memory device having cross failures can operate normally. Although the defective columns and rows of memory can be replaced with redundant rows and columns of memory, the short circuit is still present. As previously discussed, during a stand-by state, the word lines are grounded and the digit lines are balanced and precharged to a precharge voltage level. Consequently, a short circuit between a digit line and a word line provides a direct path from the precharge voltage supply to ground, and thus, places an unusually high current load on the precharge voltage supply. Where the additional current load exceeds the current drive capability of the precharge voltage supply, the voltage level of the precharge voltage supply may be reduced to below an acceptable precharge voltage level. As a result, digit lines in addition to the shorted digit line may not be sufficiently precharged, causing the memory cells of an otherwise functional digit line to fail. Even in less extreme cases where otherwise functional digit lines do not fail, or those failing can be replaced by redundant columns of memory, the additional current load caused by a digit line being short circuited to a word line results in greater power consumption.
One conventional approach taken to limit the current load on a precharge voltage supply in the event of a cross failure is to couple a diode-coupled depletion n-channel MOS (NMOS) transistor between the precharge voltage supply and the precharge circuit of a column of memory. The depletion NMOS transistor behaves as a current limiting device designed to limit the maximum current load on the precharge voltage supply to an acceptable level that allows for sufficient precharging of the digit lines. A more detailed description of this conventional approach can be found in Kirihata et al., “Fault-Tolerant Designs for 256 Mb DRAM,” IEEE J. Solid-State Circuits, vol. 31, pp. 558-66, April 1996. Although the previously described approach is effective, formation of the depletion NMOS requires an additional depletion implant step as part of the fabrication process. Adding process steps is generally considered undesirable because it necessarily results in reduced fabrication throughput.
Therefore, there is a need for an alternative approach to limiting the current load on a voltage supply in the event an unusually high current load is caused by an otherwise repairable defect.